这是龙芯 CPU AUL 模块 的指令集一小部分
cpu_gs232/blob/master/global.h
/*Fix point operation*/
`define OP_CLO 8'H00
`define OP_CLZ 8'H01
`define OP_EXT 8'H02
`define OP_INS 8'H03
`define OP_WSBH 8'H04
`define OP_ROTR 8'H06 //include ROTRV
`define OP_SEB 8'H08
`define OP_SEH 8'H09
`define OP_MOVN 8'H0a
`define OP_MOVZ 8'H0b
`define OP_MFHI 8'H0c
`define OP_MFLO 8'H0d
`define OP_MTHI 8'H0e
`define OP_MTLO 8'H0f
`define OP_MUL 8'H10
`define OP_SLL 8'H11 //include NOP,SSNOP,EHB,SLLV
`define OP_SRL 8'H12 //SRLV
`define OP_SRA 8'H13
`define OP_MULT 8'H14
`define OP_MULTU 8'H15
`define OP_DIV 8'H16
`define OP_DIVU 8'H17
`define OP_ADD 8'H18 //ADDI
`define OP_ADDU 8'H19 //ADDIU, LUI, RDPGPR, WRPGPR
`define OP_SUB 8'H1a
`define OP_SUBU 8'H1b
`define OP_AND 8'H1c //ANDI
`define OP_OR 8'H1d //ORI
`define OP_XOR 8'H1e //XORI
`define OP_NOR 8'H1f
`define OP_TEQ 8'H20 //TEQI
`define OP_TNE 8'H21 //TNEI
`define OP_TLT 8'H22 //TLTI
`define OP_TLTU 8'H23 //TLTIU
`define OP_TGE 8'H24 //TGEI`
`define OP_TGEU 8'H25 //TEEI
`define OP_SLT 8'H26 //SLTI
`define OP_SLTU 8'H27 //SLTIU
`define OP_MADD 8'H28
`define OP_MADDU 8'H29
`define OP_MSUB 8'H2a
`define OP_MSUBU 8'H2b
`define OP_J 8'H2c
`define OP_JR 8'H2d //JR.HB
`define OP_JAL 8'H2e
`define OP_JALR 8'H2f //JALR.HB
`define OP_BEQ 8'H30
`define OP_BNE 8'H31
`define OP_BLEZ 8'H32
`define OP_BGTZ 8'H33
`define OP_BLTZ 8'H34
`define OP_BGEZ 8'H35
`define OP_BLTZAL 8'H36
`define OP_BGEZAL 8'H37
`define OP_BEQL 8'H38
`define OP_BNEL 8'H39
`define OP_BLEZL 8'H3a
`define OP_BGTZL 8'H3b
`define OP_BLTZL 8'H3c
`define OP_BGEZL 8'H3d
`define OP_BLTZALL 8'H3e
`define OP_BGEZALL 8'H3f
cpu_gs232/blob/master/godson_alu_module.v
reg [31:0]bresult;
always @(sub_op or bsum_0 or bsum_1 or bsum_2 or bsum_3 or a or b or blt or eq_4 or op
or braddu_temp or pick_0 or pick_1 or pick_2 or pick_3) begin
case(op) // synopsys full_case parallel_case
/*ADDU.QB*/
`OP_ADDQ :
bresult = {bsum_3[7:0],bsum_2[7:0],bsum_1[7:0],bsum_0[7:0]};
/*ADDU_S.QB*/
`OP_ADDQ_S :
bresult = {bsum_3[8] ? 8'hff : bsum_3[7:0], bsum_2[8] ? 8'hff : bsum_2[7:0],
bsum_1[8] ? 8'hff : bsum_1[7:0], bsum_0[8] ? 8'hff : bsum_0[7:0]};
`OP_SUBQ :
/*SUBU.QB*/
bresult = {bsum_3[7:0],bsum_2[7:0],bsum_1[7:0],bsum_0[7:0]};
`OP_SUBQ_S :
/*SUBU_S.QB*/
bresult = {bsum_3[8] ? 8'h00 : bsum_3[7:0],
bsum_2[8] ? 8'h00 : bsum_2[7:0],
bsum_1[8] ? 8'h00 : bsum_1[7:0],
bsum_0[8] ? 8'h00 : bsum_0[7:0]};
`OP_RADDU :
//bresult = {22'b0, braddu_temp}; nomatch
bresult = {21'b0, braddu_temp};
`OP_CMP_EQ :
/*CMPGU.EQ.QB , CMPU.EQ.QB*/
bresult = {28'h0, eq_4[3], eq_4[2],eq_4[1],eq_4[0]};
`OP_CMP_LT :
/*CMPGU.LT.QB , CMPU.LT.QB*/
bresult = {28'h0, blt[3], blt[2], blt[1], blt[0]};
//8'hde :
`OP_CMP_LE :
/*CMPGU.LE.QB , CMPU.LE.QB*/
bresult = {28'h0, (blt[3]|eq_4[3]), (blt[2]|eq_4[2]), (blt[1]|eq_4[1]), (blt[0]|eq_4[0])};
`OP_PICK :
bresult = {pick_3, pick_2, pick_1, pick_0};
`OP_PRECEQU_PH_QBL :
/*PRECEQU_PH_QBL*/
bresult = {{1'b0, a[31:24], 7'b0}, {1'b0, a[23:16], 7'b0}};
`OP_PRECEQU_PH_QBR :
/*PRECEQU_PH_QBR*/
bresult = {{1'b0, a[15:8], 7'b0}, {1'b0, a[7:0], 7'b0}};
`OP_PRECEQU_PH_QBLA :
/*PRECEQU_PH_QBLA*/
bresult = {{1'b0, a[31:24], 7'b0}, {1'b0, a[15:8], 7'b0}};
`OP_PRECEQU_PH_QBRA :
/*PRECEQU_PH_QBRA*/
bresult = {{1'b0, a[23:16], 7'b0}, {1'b0, a[7:0], 7'b0}};
`OP_PRECEU_PH_QBL :
/*PRECEU_PH_QBL*/
bresult = {{8'b0, a[31:24]}, {8'b0, a[23:16]}};
`OP_PRECEU_PH_QBR :
/*PRECEU_PH_QBR*/
bresult = {{8'b0, a[15:8]}, {8'b0, a[7:0]}};
`OP_PRECEU_PH_QBLA :
/*PRECEU_PH_QBLA*/
bresult = {{8'b0, a[31:24]}, {8'b0, a[15:8]}};
`OP_PRECEU_PH_QBRA :
/*PRECEU_PH_QBRA*/
bresult = {{8'b0, a[23:16]}, {8'b0, a[7:0]}};
// `OP_REPL :
/*REPL(V).QB*/
default :
bresult = {a[7:0], a[7:0], a[7:0], a[7:0]};
endcase
end //end always
Select Language